View LTC3785_4731766.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FEATURES

LTC3785 10V, High Efficiency, Synchronous, No RSENSE Buck-Boost Controller DESCRIPTIO
TM
Single Inductor Architecture Allows VIN Above, Below or Equal to VOUT 2.7V to 10V Input and Output Range Up to 96% Efficiency Up to 10A of Output Current All N-Channel MOSFETs, No RSENSE True Output Disconnect During Shutdown Programmable Current Limit and Soft-Start Optional Short-Circuit Shutdown Timer Output Overvoltage and Undervoltage Protection Programmable Frequency: 100kHz to 1MHz Selectable Burst Mode(R) Operation Available in 24-Lead (4mm x 4mm) Exposed Pad QFN Package
The LTC(R)3785 is a high power synchronous buck-boost controller that drives all N-channel power MOSFETs from input voltages above, below and equal to the output voltage. With an input range of 2.7V to 10V, the LTC3785 is well suited for a wide variety of single or dual cell Li-Ion or multi-cell alkaline/NiMH applications. The operating frequency can be programmed from 100kHz to 1MHz. The soft-start time and current limit are also programmable. The soft-start capacitor doubles as the fault timer which can program the IC to latch off or recycle after a determined off time. Burst Mode operation is user controlled and can be enabled by driving the MODE pin high. Protection features include foldback current limit, shortcircuit and overvoltage protection.
, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.
APPLICATIO S

Palmtop Computers Handheld Instruments Wireless Modems Cellular Telephones
TYPICAL APPLICATIO
VOUT VIN VCC ISVIN VSENSE TG1 VBST1 FB SW1 ISSW1 VDRV BG1 LTC3785 ISVOUT TG2
4.7F
VIN 2.7V TO 10V
22F
100
Efficiency vs Input Voltage
VOUT = 3.3V FOSC = 500kHz
4.7H
EFFICIENCY (%)
95 ILOAD = 2A ILOAD = 1A 90
VC RT
MODE
VOUT 3.3V 5A
VBST2 RUN/SS ILSET CCM GND SW2 ISSW2 BG2 100F
85 2.5 4 5.5 VIN (V)
3785 TA01b
3785 TA01a
U
U
U
7
8.5
10
3785f
1
LTC3785 ABSOLUTE
(Note 1)
AXI U RATI GS
Input Supply Voltage (VIN) ......................... -0.3V to 11V ISVOUT, ISVIN .............................................. -0.3V to 11V SW1, SW2, ISSW1, ISSW2 Voltage: DC............................................................. -1V to 11V Pulsed, <1s ............................................. -2V to 12V RUN/SS, MODE, CCM, VDRV, VCC Voltages ...... -0.3V to 6V TG1, VBST1 Voltages................................... -0.3V to 16V With Respect to SW1 ............................... -0.3V to 6V TG2, VBST2 Voltages................................... -0.3V to 16V With Respect to SW2 ............................... -0.3V to 6V BG1, BG2 Voltage ........................................ -0.3V to 6V Peak Driver Output Current < 10s (TG1, TG2, BG1, BG2).................................................3A VCC Average Output Current .................................100mA Operating Temperature Range ................. -40C to 85C Storage Temperature Range................... -65C to 125C
VBST1
ISVIN
24 23 22 21 20 19 RUN/SS 1 VC 2 FB 3 VSENSE 4 ILSET 5 CCM 6 7 RT 8 MODE 9 10 11 12 ISVOUT VBST2 TG2 NC 25 18 ISSW1 17 BG1 16 VDRV 15 BG2 14 ISSW2 13 SW2
UF PACKAGE 24-LEAD (4mm x 4mm) PLASTIC QFN TJMAX = 125C, JA = 40C/W 1 LAYER BOARD, JA = 30C/W 4 LAYER BOARD EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC3785EUF#PBF LEAD BASED FINISH LTC3785EUF TAPE AND REEL LTC3785EUF#TRPBF TAPE AND REEL LTC3785EUF#TR PART MARKING 3785 PART MARKING 3785 PACKAGE DESCRIPTION 24-Lead (4mm x 4mm) Plastic QFN PACKAGE DESCRIPTION 24-Lead (4mm x 4mm) Plastic QFN TEMPERATURE RANGE -40C to 85C TEMPERATURE RANGE -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
PARAMETER VIN Supply Input Operating Voltage Quiescent Current--Burst Mode Operation Quiescent Current--Shutdown Quiescent Current--Active Error Amp Feedback Voltage Feedback Input Current Error Amp Source Current Error Amp Sink Current Error Amp AVOL Overvoltage Threshold (Note 5) (Note 5)
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = VOUT = VDRV = VBST1 = VBST2 = 3.6V, RT = 49.9k, RILSET = 59k.
CONDITIONS
MIN 2.7
SW1
TG1
VCC
VIN
VC = 0V, MODE = 3.6V (Note 4) RUN/SS = 0V, VOUT = 0V MODE = 0V (Note 4)
VSENSE Pin. % Above FB
2
U
WW
W
PIN CONFIGURATION
TOP VIEW
TYP
MAX 10
UNITS V A A mA V nA A A dB
86 15 0.8 1.200 1.225 1 -500 900 90
200 25 1.5 1.25 500
6
10
14
%
3785f
LTC3785 ELECTRICAL CHARACTERISTICS
PARAMETER Undervoltage Threshold VSENSE Input Current VCC Regulator VCC Maximum Regulating Voltage VCC Regulation Voltage VCC Regulator Sink Current Run/Soft-Start RUN/SS Threshold RUN/SS Input Current RUN/SS Discharge Current Current Limit Current Limit Sense Threshold Reverse Current Limit Sense Threshold Input Current ISVIN to ISSW1, RILSET = 121k ISVIN to ISSW1, RILSET = 59k ISSW2 to ISVOUT, CCM > 2V ISSW2 to ISVOUT, CCM < 0.4V ISVIN ISVOUT ISSW1, ISSW2

The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = VOUT = VDRV = VBST1 = VBST2 = 3.6V, RT = 49.9k, RILSET = 59k.
CONDITIONS VSENSE Pin. % Below FB VSENSE = Measured FB Voltage VIN = 5V, IVCC = -20mA VIN = 3.6V, IVCC = -20mA VOUT = VCC = 5V When IC is Enabled When EA is at Maximum Boost Duty Cycle RUN/SS = 0V During Current Limit 20 55 -50

MIN -3.5
TYP -6.5 1
MAX -9.5 500 4.55 3.6
UNITS % nA V V A
4.15 3.3
4.35 3.5 800
0.35
0.7 1.9 -1 1 60 105 -110 -15 80 10 0.1
1.1
V V A A mV mV mV mV A A A V V A V A s
5 100 155 -170 -35 150 20 5 0.4
CCM Input Threshold (High) CCM Input Threshold (Low) CCM Input Current Burst Mode Operation Mode Threshold Mode Input Current tON Time Oscillator Frequency Accuracy Switching Characteristics Maximum Duty Cycle TG1, TG2 Driver Impedance BG1, BG2 Driver Impedance TG1, TG2 Rise Time BG1, BG2 Rise Time TG1, TG2 Fall Time BG1, BG2 Fall Time Buck Driver Nonoverlap Time Boost Driver Nonoverlap Time CLOAD = 3300pF (Note 3) CLOAD = 3300pF (Note 3) CLOAD = 3300pF (Note 3) CLOAD = 3300pF (Note 3) TG1 to BG1 TG2 to BG2 Boost (% Switch BG2 On) Buck (% Switch TG1 On)
2.2 0.01 1 2.2 1
0.8
1.5 0.01 1.4
370 80
509 90 99 2 2 20 20 20 20 100 100
650
kHz % % ns ns ns ns ns ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3785E is guaranteed to meet performance specifications from 0C to 85C. Specifications over -40C to 85C operating
temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Specification is guaranteed by design and not 100% tested in production. Note 4: Current measurements are performed when the outputs are not switching. Note 5: The IC is tested in a feedback loop to make the measurement.
3785f
3
LTC3785 TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25C unless otherwise noted)
Li-Ion to 3.3V Efficiency vs Load Current
100 90 80 EFFICIENCY (%) EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.0001 0.001 VIN = 4.2V VIN = 3.6V VIN = 3V MOSFET Si7940 L = 4.7H WURTH WE-PD fOSC = 500kHz 0.1 0.01 LOAD CURRENT (A) 1 10
3785 G01
Burst Mode OPERATION
FIXED FREQUENCY
60 50 40 30 20 10 0 0.0001 0.001
FIXED FREQUENCY
EFFICIENCY (%)
Burst Mode Ripple
VOUT 500mV/ DIV VIN 3V TO 8.5V
VOUT 50mV/DIV AC COUPLED INDUCTOR CURRENT 1A/DIV VOUT = 3.3V COUT = 100F 5s/DIV
3785 G04
VFB vs Temperature
1.2255 1.2250 CHANGE FROM 25C (%) 1.2245 1.2240 VFB (V) 1.2235 1.2230 1.2225 1.2220 1.2215 1.2210 -50 -25 50 25 0 TEMPERATURE (C) 75 100
3785 G07
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -50
OSCILLATOR FREQUENCY (kHz)
4
UW
Two Li-Ion to 7V Efficiency vs Load Current
100 90 80 70 Burst Mode OPERATION 100 90 80 70 60 50 40 30 20 10
Li-Ion/9V to 5V VOUT Efficiency vs Load Current
Burst Mode OPERATION
FIXED FREQUENCY VIN = 9V VIN = 4.2V VIN = 3.6V VIN = 2.7V MOSFET Si7940 L = 5.6H MSS1260 fOSC = 430kHz 0.001 0.01 0.1 LOAD CURRENT (A) 1 10
3785 G02
VIN = 8.4V VIN = 7.2V VIN = 5.4V MOSFET Si7940 L = 5.6H MSS1260 fOSC = 430kHz 0.01 0.1 LOAD CURRENT (A) 1 10
3785 G02
0 0.0001
Line Transient Response
VOUT 200mV/ DIV
VOUT Load Transient
ILOAD = 300mA VOUT = 5V COUT = 100F
500s/DIV
3785 G05
ILOAD 10mA TO 2A VIN = 3.6V VOUT = 3.3V COUT = 100F 100s/DIV
3785 G06
Normalized Oscillator Frequency vs Temperature
1.0 0.8 1000 800 600 400 200 0 -25 25 50 0 TEMPERATURE (C) 75 100
3785 G08
Oscillator Frequency vs RT
1200
20
40
60 RT (k)
80
100
3785 G09
3785f
LTC3785 TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25C unless otherwise noted)
VIN Start-Up Voltage vs Temperature
2.490 100
VIN START-UP VOLTAGE (V)
2.485 VIN CURRENT (A)
THRESHOLD (V)
2.480
2.475
2.470
2.465 -50
-25
0 25 50 TEMPERATURE (C)
PI FU CTIO S
RUN/SS (Pin 1): Run Control and Soft-Start Input. An internal 1A charges the soft-start capacitor and will charge to approximately 2.5V. During a current limit fault, the soft-start capacitor will incrementally discharge. Once the pin drops below 1.225V the IC will enter fault mode, turning off the outputs for 32 times the soft-start time. If >5A (at RUN/SS = 1.225V) is applied externally, the part will latch off after a fault is detected. If >40A (at RUN/SS = 1.225V) is applied externally, current limit faults will not discharge the SS capacitor. VC (Pin 2): Error Amp Output. A frequency compensation network is connected from this pin to the FB pin to compensate the loop. See the section "Closing the Feedback Loop" for guidelines. FB (Pin 3): Feedback Pin. Connect resistor divider tap here. The feedback reference voltage is typically 1.225V The output voltage can be adjusted from 2.7V to 10V according to the following formula: VOUT = 1.225V * R1 + R2 R2 VSENSE (Pin 4): Overvoltage and Undervoltage Sense. The overvoltage threshold is internally set 10% above the regulated FB voltage and the undervoltage threshold is internally set 6.5% below the FB regulated voltage. This pin can be tied to FB but to optimize the response time it is recommended that a voltage divider from VOUT be applied. The divider can be skewed from the feedback value to achieve the desired UV or OV threshold. ILSET (Pin 5): Current Limit Set. A resistor from this pin to ground sets the current limit threshold from the ISVIN and ISSW1 pins. CCM (Pin 6): Continuous Conduction Mode Control Pin. When set low, the inductor current is allowed to go slightly negative (-15mV referenced to the ISVOUT - ISSW2 pins). When driven high, the reverse current limit is set to the similar value of the forward current limit set by the ILSET pin. RT (Pin 7): Oscillator Programming Pin. A resistor from this pin to GND sets the free-running frequency of the IC. fOSC 2.5e10/RT.
UW
75
3785 G10
VIN Burst Quiescent Current vs Temperature
12 10 95 8 6 4 2 0 -2 -4 -6 100 80 -50 -25 25 50 0 TEMPERATURE (C) 75 100
3785 G11
OV and UV Thresholds vs Temperature
OV THRESHOLD
90
85
UV THRESHOLD
-8 -50
-25
25 50 0 TEMPERATURE (C)
75
100
3785 G12
U
U
U
3785f
5
LTC3785 PI FU CTIO S
MODE (Pin 8): Burst Mode Control Pin. * MODE = High: Enable Burst Mode Operation. In Burst Mode operation the operation is variable frequency, which provides a significant efficiency improvement at light loads. The Burst Mode operation will continue until the pin is driven low. * MODE = Low: Disable Burst Mode operation and maintain low noise, constant frequency operation. NC (Pin 9): No Connect. There is no electrical connection to this pin inside the package. ISVOUT (Pin 10): Reverse Current Limit Comparator Noninverting Input. This pin is normally connected to the drain of the N-channel MOSFET D (TG2 driven). VBST2 (Pin 11): Boosted Floating Driver Supply for Boost Switch D. This pin will swing from a diode below VCC up to VOUT + VCC - VDIODE. SW2 (Pin 13): Ground Reference for Driver D. Gate drive from TG2 will reference to the common point of output switches C and D. ISSW2 (Pin 14): Reverse Current Limit Comparator Inverting Input. This pin is normally connected to the source of the N-channel MOSFET D (TG2 driven). VDRV (Pin 16): Driver Supply for Ground Referenced Switches. Connect this pin to VCC potential. BG1, BG2 (Pins 17, 15): Bottom gate driver pins drive the ground referenced N-channel MOSFET switches B and C. ISSW1 (Pin 18): Forward Current Limit Comparator Noninverting Input. This pin is normally connected to the source of the N-channel MOSFET A (TG1 driven). SW1 (Pin 19): Ground Reference for Driver A. Gate drive from TG1 will reference to the common point of output switches A and B. TG1, TG2 (Pins 20, 12): Top gate drive pins drive the top N-channel MOSFET switches A and D with a voltage swing equal to VCC - VDIODE superimposed on the SW1 and SW2 nodes respectively. VBST1 (Pin 21): Boosted Floating Driver Supply for the Buck Switch A. This pin will swing from a diode below VCC up to VIN + VCC - VDIODE. ISVIN (Pin 22): Forward Current Limit Comparator Inverting Input. This pin is normally connected to the drain of N-channel MOSFET A (TG1 driven). VCC (Pin 23): Internal 4.5V LDO Regulator Output. The driver and control circuits are powered from this voltage to limit the maximum VGS drive voltage. Decouple this pin to power ground with at least a 4.7F ceramic capacitor. For low VIN applications, VCC can be bootstrapped from VOUT through a Schottky diode. VIN (Pin 24): Input Supply Pin for the VCC Regulator. A ceramic capacitor of at least 10F is recommended close to the VIN and GND pins. Exposed Pad (Pin 25): The GND and PGND pins are connected to the Exposed Pad which must be connected to the PCB ground for electrical contact and rated thermal performance.
6
U
U
U
3785f
LTC3785 BLOCK DIAGRA
1.225V
+ - + -
VBE
CSS 1 RUN/SS
1A V = 60k/RILSET 2A ADRV ILIM(OUT) ILIM(OUT) 10A MAX IMAX
VOUT +10% 4 VOUT R1 R2 CP1 3 2 RT 7 FB VC 1.225V VSENSE
+ -
SW2 PULSE
BBM SW2 DELAY
TG2 BG2 DISABLE
15mV OR 1X ILIMIT
REVERSE LIMIT
RT
REVERSE CURRENT LIMIT (ZERO LIMIT FOR BURST) OSC DDRV
VREV TG2 VBST2
1 = Burst Mode OPERATION 0 = FIXED FREQUENCY BURST LOGIC BURST SAMPLED VDRV SS
1.5V 8 MODE
RILSET 5
ILSET
ILIMIT SET
ILIM COMP IMAX COMP
CDRV PGND VREV GND/PGND 25 0 = 15mV 1 = ILIMIT
1/2 LIMIT AT VOUT < 1V CCM 6
+ -
- +
W
VIN 2.7V TO 10V 24 FAULT LOGIC VIN TSD 1.225V VREF 4.5V REG IDEAL DIODE 2.4V 1/25k 100% DUTY CHARGE PUMP VCC ISVIN 23 22 CVCC RUN UVLO
+ -
ILIMIT
gm
+ -
TG1
20 21 CA 19 18 16 17
MA
CIN
+ -
V = 90k/RILSET BBM SW1 DELAY TG1 BG1
+ X10 -
VBST1 SW1 ISSW1 VDRV BG1
SW1
-6.5%
+ - - +
UV
SW1 PULSE UV BDRV
SAMPLED
D1 OPT
MB
OV
OV
VOUT LOW
1.8V PGND 100% DUTY CHARGE PUMP L1 ISVOUT
10 D2 OPT 12 11 MD
VOUT
SW2 ISSW2
CB 13 14 SW2
+ -
BG2
15
MC
COUT
3785 BD
3785f
7
LTC3785 OPERATIO
MAIN CONTROL LOOP The LTC3785 is a buck-boost voltage mode controller that provides an output voltage above, equal to or below the input voltage. The LTC proprietary topology and control architecture also employs drain-to-source sensing (No RSENSE) for forward and reverse current limiting. The controller provides all N-channel MOSFET output switch drive, facilitating single package multiple power switch technology along with lower RDS(ON). The error amp output voltage (VC) determines the output duty cycle of the switches. Since the VC pin is a filtered signal, it provides rejection of high frequency noise. The FB pin receives the voltage feedback signal, which is compared to the internal reference voltage by the error amplifier. The top MOSFET drivers are biased from a floating bootstrap capacitor, which is normally recharged during each off cycle through an external diode when the top MOSFET turns off. Optional Schottky diodes can be connected across synchronous switch B and D to provide a lower drop during the dead time and eliminate efficiency loss due to body diode reverse recovery. The main control loop is shut down by pulling the RUN/ SS pin low. An internal 1A current source charges the RUN/SS pin and when the pin voltage is higher than 0.7V the IC is enabled. The VC voltage is then clamped to the RUN/SS voltage minus 0.7V while CSS is slowly charged during start-up. This "soft-start" clamping prevents inrush current draw from the input power supply. POWER SWITCH CONTROL Figure 1 shows a simplified diagram of how the four power switches are connected to the inductor, VIN, VOUT and GND. Figure 2 shows the regions of operation for the LTC3785 as a function of duty cycle D. The power switches are properly controlled so that the transfer between modes is continuous. Buck Region (VIN > VOUT) Switch D is always on and switch C is always off during buck mode. When the error amp output voltage, VC, is approximately above 0.1V, output A begins to switch. During
TG1
8
U
VIN VOUT A SW1 BG1 B L SW2 C BG2 D TG2
3785 F01
Figure 1. Output Switch Configuration
90% DMAX BOOST A ON, B OFF PWM C, D SWITCHES DMIN BOOST DMAX BUCK FOUR SWITCH PWM D ON, C OFF PWM A, B SWITCHES DMIN BUCK BUCK/BOOST REGION BOOST REGION
BUCK REGION
3785 F02
Figure 2. Operation Mode vs VC Voltage
the off time of switch A, synchronous switch B turns on for the remainder of the switching period. Switches A and B will alternate similar to a typical synchronous buck regulator. As the control voltage increases, the duty cycle of switch A increases until the max duty cycle of the converter in buck mode reaches DMAX_BUCK, given by: DMAX_BUCK = 100 - D4(SW)% where D4(SW) = duty cycle % of the four switch range. D4(SW) = (300ns * f) * 100% where f = operating frequency, Hz. Beyond this point the "four switch" or buck-boost region is reached. If during the rectification phase (switch pair BD on) the inductor current becomes discontinuous, then switch B is turned off and a damping impedance is connected across the inductor to prevent ringing. Buck-Boost or Four Switch (VIN ~ VOUT) When the error amp output voltage, VC, is above approximately 0.65V, switch pair AD remain on for duty cycle DMAX_BUCK, and the switch pair AC begin to phase in. As switch pair AC phases in, switch pair BD phases out
3785f
LTC3785 OPERATIO
accordingly. When the VC voltage reaches the edge of the buck-boost range, approximately 0.7V, the AC switch pair completely phase out the BD pair, and the boost phase begins at duty cycle, D4(SW). The input voltage, VIN, where the four switch region begins is given by: VIN = VOUT V 1 - ( 300ns * f )
the point at which the four switch region ends is given by: VIN = VOUT(1 - D) = VOUT(1 - 300ns * f) V If during the rectification phase (switch pair BD on) the inductor current becomes discontinuous, then switch D is turned off and a damping impedance is connected across the inductor to prevent ringing. Boost Region (VIN < VOUT) Switch A is always on and switch B is always off during boost mode. When the error amp output voltage, VC, is approximately above 0.7V, switch pair C and D will alternately switch to provide a boosted output voltage. This operation is typical to a synchronous boost regulator. The maximum duty cycle of the converter is limited to 90% typical. If during the rectification phase (switch pair AD on) the inductor current becomes discontinuous then switch D is turned off and a damping impedance is connected across the inductor to prevent ringing. Burst Mode OPERATION During Burst Mode operation, the LTC3785 delivers energy to the output until it is regulated and then goes into a sleep state where the outputs are off and the IC is consuming only 86A. In Burst Mode operation, the output ripple has a variable frequency component, which is dependent upon load current During the period where the converter is delivering energy to the output, the inductor will reach a peak current
U
determined by an on time, tON, and will terminate at zero current for each cycle. The on time is given by: tON = 2.4 VIN * f where f is the oscillator frequency. The peak current is given by: IPEAK = IPEAK = VIN * tON L 2.4 f *L So the peak current is independent of VIN and inversely proportional to the f * L product optimizing the energy transfer for various applications. In Burst Mode operation the maximum output current is given by: IOUT(MAX,BURST) 1.2 * VIN A f * L * VOUT + VIN
(
)
Burst Mode operation is user-controlled by driving the MODE pin high to enable and low to disable. VCC REGULATOR An internal P-channel low dropout regulator produces 4.35V at the VCC pin from the VIN supply pin. VCC powers the drivers and internal circuitry of the LTC3785. The VCC pin regulator can supply a peak current of 100mA and must be bypassed to ground with a minimum of 4.7F placed directly adjacent to the VCC and GND pins. Good bypassing is necessary to supply the high transient current required by the MOSFET gate drivers and to prevent interaction between channels. If desired, the VCC regulator can be connected to VOUT through a Schottky diode to provide higher gate drive in low input voltage applications. The VCC regulator can also be driven with an external 5V source directly (without a Schottky diode).
3785f
9
LTC3785 OPERATIO
TOPSIDE MOSFET DRIVER SUPPLY (VBST1, VBST2) The external bootstrap capacitors connected to the VBST1 and VBST2 pins supply the gate drive voltage for the topside MOSFET switches A and D. When the top MOSFET switch A turns on, the switch node SW1 rises to VIN and the VBST2 pin rises to approximately VIN + VCC. When the bottom MOSFET switch B turns on, the switch node SW1 drops low and the boost capacitor is charged through the diode connected to VCC. When the top MOSFET switch D turns on, the switch node SW2 rises to VOUT and the VBST2 pin rises to approximately VOUT + VCC. When the bottom MOSFET switch C turns on, the switch node SW2 drops low and the boost capacitor is charged through the diode connected to VCC. The boost capacitors need to store about 100 times the gate charge required by the top MOSFET switch A and D. In most applications a 0.1F to 0.47F, X5R or X7R dielectric capacitor is adequate. RUN/SOFT-START (RUN/SS) The RUN/SS pin serves as the enable to the LTC3785, soft-start function, and fault programming. A 1A current source charges the external capacitor. Once the RUN/SS voltage is above a diode drop(~0.7V) the IC is enabled. Once the IC is enabled, the RUN/SS voltage minus a diode drop (RUN/SS - 0.7V) clamps the output of the error amp (VC) to limit duty cycle. The range of the duty cycle clamping is approximately 0.7V to 1.7V. The RUN/SS pin is clamped to approximately 2.2V. If current limit is reached the pin will begin to discharge with a current determined by the magnitude of inductor current overcurrent limit, but not to exceed 10A. This function will be described in more detail in the "Forward Current Limit" section. OSCILLATOR The frequency of operation is set through a resistor from the RT pin to ground where f (2.5e10/RT)Hz. ERROR AMP The error amplifier is a voltage mode amplifier with a reference voltage of 1.225V internally connected to the non-inverting input. The loop compensation components
10
U
are configured around the amplifier to provide loop compensation for the converter. The RUN/SS pin will clamp the error amp output, VC, to provide a soft-start function. UNDERVOLTAGE AND OVERVOLTAGE PROTECTION The LTC3785 incorporates overvoltage (OV) and undervoltage (UV) functions for fault protection and transient limitation. Both comparators are connected to the VSENSE pin, which usually has a similar voltage divider as the error amplifier without the compensation. The overvoltage threshold is 10% above the reference. The undervoltage threshold is 6.5% below the reference with both comparators having 1% hysteresis. During an overvoltage fault, all output switching stops until the fault ceases. During an undervoltage fault, the IC is commanded to run fixed frequency only (disabled Burst Mode operation). If the design requires a tightened threshold to one of the comparator thresholds the voltage divider on the VSENSE pin can be skewed to achieve the threshold. Since the range is a constant, tightening the UV threshold will loosen the OV threshold and vice versa. FORWARD CURRENT LIMIT The LTC3785 is designed to sense the input current by sampling the voltage across MOSFET A during the on time of the switch (TG1 = High). The sense pins are ISVIN and ISSW1. A current sense resistor can be used if increased accuracy is required. The current limit threshold can be programmed with a resistor on the ILSET pin. Once the desired current limit has been chosen, RILSET can be determined by the following formula: RILSET = 6000 RDS(ON)A * ILIMIT where RDS(ON)A = RDS(ON) of N-channel MOSFET switch A and ILIMIT = current limit in Amps. Once the voltage between ISVIN and ISSW1 exceeds the threshold, current will be sourced out of FB to take control of the voltage loop, resulting in a lower output voltage to regulate the input current. This fault condition causes the RUN/SS capacitor to begin discharging. The level of
3785f
LTC3785 OPERATIO
the discharge current depends on how much the current exceeds the programmed threshold. Figure 3 is a simplified diagram of the current sense and fault circuitry. If the current limit fault duration is long enough to discharge the RUN/SS capacitor below 1.225V, the fault latch is set and will cycle the RUN/SS capacitor 16 times (1A charging and 1A discharging of the RUN/SS capacitor) to create an off time of 32 times the soft-start time before the outputs are allowed to switch to restart the output voltage. If the current limit fault level exceeds 150% of the programmed ILIMIT level at any time, the IMAX comparator is tripped and output switches B and D are turned on to discharge the inductor current for the remainder of the cycle. To have the power converter latch-off on a fault, a pull-up current between 4A and 7A on the RUN/SS pin will allow the RUN/SS capacitor to discharge during an extended fault, but will prevent cycling of the fault which will cause the converter to stay off. One method to implement this is by placing a diode (anode tied to VOUT) and a resistor from VOUT to the RUN/SS pin. The current sourced into RUN/SS will be
THERMAL SD 1.225V
0.7V
1A 1 CSS RUN/SS 2.2V 2A 1/3 * ILIM(OUT) 10A MAX TURN SWITCHES B AND D ON
1 VOUT R1 CP1 3 2 R2 FB VC 1.225V
+ -
ERROR AMP
SWITCH D OFF REVERSE CURRENT LIMIT
6 RILSET
ILSET
ILIMIT SET
ILIM COMP IMAX COMP
Figure 3. Block Diagram of Current Limit Fault Circuitry
3785f
- +
+ -
U
VOUT - 0.7 divided by the resistor value. To ignore all faults source greater than 40A into the RUN/SS pin (At 1.225V on the RUN/SS pin). Since the maximum fault current is limited, this will prevent any discharging of the RUN/SS capacitor, the soft-start capacitor will need to be sized accordingly to accommodate the extra charging current at start-up. During an output short-circuit or if VOUT is less than 1.8V, the current limit folds back to 50% of the programmed level. REVERSE CURRENT LIMIT The LTC3785 can be programmed to provide full class D operation or allowed to source and sink current equal to the current limit set value. This is achieved by asserting a high level on the CCM pin. To minimize the reverse output current, the CCM pin should be driven low or strapped to ground. During this mode only, -15mV typical is allowed across output switch D and is sensed with the ISVOUT and ISSW2 pins.
+ -
S FAULT S LOGIC ILIMIT COMP gm = 1/20k
+ gm -
ISVIN
VIN 22 A
RUN
V = 60k/RILSET (15k/RILSET WHEN VOUT < 1.8V) IMAX COMP
TG1 20
SW1 19
+ -
V = 90k/RILSET
+ X10 -
SAMPLED
ISSW1
18
BG1 17 CCM = HIGH = 6k/RILSET CCM 6 CCM = LOW = 15mV
B L1
ILIM(OUT) 30A MAX
-
+
ISVOUT
10 D
VOUT COUT
TG2 12
SW2 13 SAMPLED ISSW2
14 C
3785 F03
BG2 15
11
LTC3785 APPLICATIO S I FOR ATIO
INDUCTOR SELECTION The high frequency operation of the LTC3785 allows the use of small surface mount inductors. The inductor current ripple is typically set 20% to 40% of the maximum inductor current. For a given ripple the inductance terms are given as follows: L> VIN(MIN)2 * VOUT - VIN(MIN) * 100 f * IOUT(MAX ) * %Ripple * VOUT2 VOUT * VIN(MAX ) - VOUT * 100 f * IOUT(MAX ) * %Ripple * VIN(MAX )
(
)
,(Boost Mode)
L>
(
)
,(Buck Mode)
where: f = Operating frequency, Hz %Ripple = Allowable inductor current ripple, % VIN(MIN) = Minimum input voltage (limit to VOUT/2 minimum for worst case), V VIN(MAX) = Maximum input voltage, V VOUT = Output voltage, V IOUT(MAX) = Maximum output load current, A For high efficiency choose an inductor with a high frequency core material, such as ferrite, to reduce core loses. The inductor should have low ESR (equivalent series resistance) to reduce the I2R losses, and must be able to handle the peak inductor current without saturating. Molded chokes or chip inductors usually do not have enough core to support the peak inductor currents in the 3A to 6A region. To minimize radiated noise, use a toroid, pot core or shielded bobbin inductor. CIN AND COUT SELECTION In boost mode, input current is continuous. In buck mode, input current is discontinuous. In buck mode, the selection of input capacitor, CIN, is driven by the need to filter the input square wave current. Use a low ESR capacitor, sized to handle the maximum RMS current. For buck operation, the maximum RMS capacitor current is given by: IRMS ~ IOUT(MAX ) * VOUT VIN V * 1 - OUT VIN
12
U
This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. In boost mode, the discontinuous current shifts from the input to the output, so COUT must be capable of reducing the output voltage ripple. The effects of ESR (equivalent series resistance) and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. The steady ripple due to charging and discharging the bulk capacitance is given by: VRIPPLE _ BOOST = VRIPPLE _ BUCK = IOUT(MAX ) * VOUT - VIN(MIN) COUT * VOUT * f VOUT * VIN(MAX ) - VOUT 8 * L * COUT * VIN(MAX )
W
U
U
(
)
(
* f2
)
where COUT= output filter capacitor, F The steady ripple due to the voltage drop across the ESR is given by: VBOOST,ESR = IL(MAX,BOOST) * ESR VBUCK,ESR = L * f * VIN
( VIN(MAX) - VOUT ) * VOUT * ESR
Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient. Capacitors are now available with low ESR and high ripple current ratings such as OS-CON and POSCAP. POWER N-CHANNEL MOSFET SELECTION AND EFFICIENCY CONSIDERATIONS The LTC3785 requires four external N-channel power MOSFETs, two for the top switches (switches A and D, shown in Figure 1) and two for the bottom switches (switches B and C shown in Figure 1). Important parameters for the power MOSFETs are the breakdown voltage
3785f
LTC3785 APPLICATIO S I FOR ATIO
VBR(DSS), threshold voltage VGS(TH), on-resistance RDS(ON), reverse transfer capacitance CRSS and maximum current IDS(MAX). The drive voltage is set by the 4.5V VCC supply. Consequently, logic-level threshold MOSFETs must be used in LTC3785 applications. If the input voltage is expected to drop below 5V, then sub-logic threshold MOSFETs should be considered. In order to select the power MOSFETs, the power dissipated by the device must be known. For switch A, the maximum power dissipation happens in boost mode, when it remains on all the time. Its maximum power dissipation at maximum output current is given by: V PA(BOOST) = OUT * IOUT(MAX ) * T * RDS(ON) VIN where T is a normalization factor (unity at 25C) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/C as shown in Figure 4. For a maximum junction temperature of 125C, using a value T = 1.5 is reasonable. Switch B operates in buck mode as the synchronous rectifier. Its power dissipation at maximum output current is given by: PB(BUCK) = VIN - VOUT * IOUT(MAX )2 * T * RDS(ON) VIN
2
2.0 T NORMALIZED ON-RESISTANCE
1.5
1.0
0.5
0 -50
50 100 0 JUNCTION TEMPERATURE (C)
150
3785 F04
Figure 4. Normalized RDS(ON) vs Temperature
U
Switch C operates in boost mode as the control switch. Its power dissipation at maximum current is given by:
PC(BOOST) =
W
U
U
( VOUT - VIN ) * VOUT * I
VIN2 *RDS(ON) + k * VOUT 3 *
2 OUT(MAX )
* T * CRSS * f
IOUT(MAX ) VIN
where CRSS is usually specified by the MOSFET manufacturers. The constant k, which accounts for the loss caused by reverse recovery current, is inversely proportional to the gate drive current and has an empirical value of 1.0. For switch D, the maximum power dissipation happens in boost mode when its duty cycle is higher than 50%. Its maximum power dissipation at maximum output current is given by: V PD (BOOST ) = OUT * IOUT(MAX )2 * T * RDS(ON) VIN Typically, switch A has the highest power dissipation and switch B has the lowest power dissipation unless a short occurs at the output. From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following formula: TJ = TA + P * RTH(JA) The RTH(JA) to be used in the equation normally includes the RTH(JC) for the device plus the thermal resistance from the case to the ambient temperature (RTH(CA)). This value of TJ can then be compared to the original, assumed value used in the iterative calculation process. SCHOTTKY DIODE (D1, D2) SELECTION Optional Schottky diodes D1 and D2 shown in the Block Diagram conduct during the dead time between the conduction of the power MOSFET switches. They are intended to prevent the body diode of synchronous switches B and D from turning on and storing charge during the dead time. In particular, D2 significantly reduces reverse recovery current between switch D turn off and switch C turn on, which improves converter efficiency and reduces switch C voltage stress. In order for D2 to be effective, it must be located in very close proximity to SWD.
3785f
13
LTC3785 APPLICATIO S I FOR ATIO
CLOSING THE FEEDBACK LOOP
The LTC3785 incorporates voltage mode control. The control to output gain is given by: GBuck = 1.6 * VIN,Buck Mode GBOOST = 1.6 * VOUT ,Boost Mode VIN
2
The output filter exhibits a double-pole response and is given by: 1 fFILTER _ POLE = 2 * * L * COUT where COUT is the output filter capacitor. The output filter zero is given by: fFILTER _ ZERO = 1 2 * * RESR * COUT
where RESR is the capacitor equivalent series resistance. A troublesome feature in boost mode is the right half plane zero (RHP), and is given by: VIN2 fRHPZ = 2 * * IOUT * L * VOUT The loop gain is typically rolled off before the RHP zero frequency. A simple type I compensation network (Figure 5) can be incorporated to stabilize the loop but at a cost of reduced bandwidth and slower transient response. To ensure proper phase margin, the loop must cross over almost a decade before the L-C double pole.
VOUT R1
+
ERROR AMP
1.225V FB CP1
-
VC R2
3785 F05
Figure 5. Error Amplifier with Type I Compensation
14
U
The unity gain frequency of the error amplifier with the type 1 compensation is given by: fUG = 1 2 * * R1 * CP1 Most applications demand an improved transient response to allow a smaller output filter capacitor. To achieve a higher bandwidth, type III compensation is required as shown in Figure 6. Two zeros are required to compensate for the double pole response.
W
U
U
fPOLE1 fZERO1 = fZERO2 = fPOLE2
1 (a very low frequency) 2 * * 32e3 * CP1 * R1 1 2 * * RZ * CP1 1 2 * * R1 * CZ1 1 2 * * RZ * CP2
VOUT
+
ERROR AMP
1.225V R1 FB CP1 CP2
3785 F06
CZ1
-
VC RZ R2
Figure 6. Error Amplifier with Type III Compensation
EFFICIENCY CONSIDERATIONS The percentage efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in circuits produce losses, four main sources account for most of the losses in LTC3785 application circuits:
3785f
LTC3785 APPLICATIO S I FOR ATIO
1. DC I2R losses. These arise from the resistances of the MOSFETs, sensing resistor (if used), inductor and PC board traces and cause the efficiency to drop at high output currents. 2. Transition loss. This loss arises from the brief voltage transition time of switch A or switch C. It depends upon the switch voltage, inductor current, driver strength and MOSFET capacitance, among other factors. Transition Loss ~ VSW2 * IL * CRSS * f where CRSS is the reverse transfer capacitance. 3. CIN and COUT loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator in buck mode. The output capacitor has the more difficult job of filtering the large RMS output current in boost mode. Both CIN and COUT are required to have low ESR to minimize the AC I2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. 4. Other losses. Optional Schottky diodes D1 and D2 are responsible for conduction losses during dead time and light load conduction periods. Core loss is the predominant inductor loss at light loads. Turning on switch C causes reverse recovery current loss in boost mode. When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If you make a change and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no change in efficiency. 5. VCC regulator loss. In applications where the input voltage is above 5V, such as two Li-Ion cells, the VCC regulator will dissipate some power due the differential voltage and the average output current to the drive the gates of the output switches. The VCC pin can be driven directly from a high efficiency external 5V source if desired to incrementally improve overall efficiency at lighter loads. DESIGN EXAMPLE As a design example, assume VIN = 2.7V to 10V (3.6V nominal Li-Ion with 9V adapter), VOUT = 3.3V (5%), IOUT(MAX) = 3A and f = 500kHz.
U
Determine the Inductor Value Setting the Inductor Ripple to 40% and using the equations in the Inductor Selection section gives: 500 * 103 * 3 * 40 * 10 So the worst-case ripple for this application is during buck mode so a standard inductor value of 3.3H is chosen. Determine the Proper Inductor Type Selection The highest inductor current is during boost mode and is given by: IL(MAX _ AV ) = VOUT * IOUT VIN *
W
U
U
(2.7)2 * (3.3 - 2.7) * 100 = 0.67H L> 2 500 * 103 * 3 * 40 * ( 3.3) 3.3 * (10 - 3.3) * 100 L> = 3.7H
where = estimated efficiency in this mode (use 80%). IL(MAX _ AV ) = 3.3 * 3 = 4.6 A 2.7 * 0.8
To limit the maximum efficiency loss of the inductor ESR to below 5% the equation is: ESRL(MAX ) ~ VOUT * IOUT * %Loss = 24m IL(MAX _ AV )2 * 100
A suitable inductor for this application could be a Coiltronics CD1-3R8 which has a rating DC current of 6A and ESR of 13m. Choose a Proper MOSFET Switch Using the same guidelines for ESR of the inductor, one suitable MOSFET could be the Siliconix Si7940DP which is a dual MOSFET in a surface mount package with 25m at 2.5V and a total gate charge of 12nC. Checking the power dissipation of each switch will ensure reliable operation since the thermal resistance of the package is 60C/W.
3785f
15
LTC3785 APPLICATIO S I FOR ATIO
The maximum power dissipation of switch A and C occurs in boost mode. Assuming a junction temperature of TJ = 100C with 100C = 1.3, the power dissipation at VIN = 2.7, and using the equations from the Efficiency Considerations section: 3.3 PA(BOOST) = * 3 *1.3 * 0.025 = 0.43W 2.7 PC(BOOST) =
2
(3.3 - 2.7) * 3.3 * 32 * 1.3 * 0.025
2 . 72
+ 1 * 3.33 * = 0.09 W
3 * 0.45 - 9 * 500 * 103 2.7
The maximum power dissipation of switch B and D occurs in buck mode and is given by: 10 - 3.3 2 PB(BUCK) = * 3 * 1.3 * 0.025 = 0.20 W 10 PD(BOOST) = 3.3 2 * 3 * 1.3 * 0.025 = 0.10 W 10
Now to double check the TJ of the package with 50C ambient. Since this is a dual NMOS package we can add switches A + B and C + D worst case. For applications where the MOSFETs are in separate packages each device's maximum TJ would have to be calculated. TJ(PKG1) = TA + JA(PA + PB) = 50 + 60 * (0.43 + 0.20) = 88C TJ(PKG2) = TA + JA(PC + PD) = 50 + 60 * (0.09 + 0.10) = 60C Set The Maximum Current Limit The equation for setting the maximum current limit of the IC is given by: RILSET = 6e3 RDS(ON)A * ILIMIT
16
U
The maximum current is set 25% above IL(PEAK) to account for worst-case variation at 100C = 6A. RILSET = 6e3 = 42k 0.025 * 6 Choose the Input and Output Capacitance The input capacitance should filter current ripple which is worst case in buck mode. Since the input current could reach 6A, a capacitor ESR of 10m or less will yield an input ripple of 60mV. The output capacitance should filter current ripple which is worst in boost mode, but is usually dictated by the loop response, the maximum load transient and the allowable transient response. PC BOARD LAYOUT CHECKLIST The basic PC board layout requires a dedicated ground plane layer. Also, for high current, a multilayer board provides heat sinking for power components. * The ground plane layer should not have any traces and it should be as close as possible to the layer with power MOSFETs. * Place CIN, switch A, switch B and D1 in one compact area. Place COUT, switch C, switch D and D2 in one compact area. * Use immediate vias to connect the components (including the LTC3785's GND/PGND pin) to the ground plane. Use several large vias for each power component. * Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low. * Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. Connect the copper areas to any DC net (VIN or GND). When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3785.
3785f
W
U
U
LTC3785 APPLICATIO S I FOR ATIO
* Segregate the signal and power grounds. All small-signal components should return to the GND pin at one point. The sources of switch B and switch C should also connect to one point at the GND of the IC. * Place switch B and switch C as close to the controller as possible, keeping the PGND, BG and SW traces short. * Keep the high dV/dT SW1, SW2, VBST1, VBST2, TG1 and TG2 nodes away from sensitive small-signal nodes. * The path formed by switch A, switch B, D1 and the CIN capacitor should have short leads and PC trace lengths. The path formed by switch C, switch D, D2 and the COUT capacitor also should have short leads and PC trace lengths. * The output capacitor (-) terminals should be connected as close as possible to the (-) terminals of the input capacitor. * Connect the VCC decoupling capacitor CVCC closely to the VCC and PGND pins.
U
* Connect the top driver boost capacitor CA closely to the VBST1 and SW1 pins. Connect the top driver boost capacitor CB closely to the VBST2 and SW2 pins. * Connect the input capacitors CIN and output capacitors COUT close to the power MOSFETs. These capacitors carry the MOSFET AC current in boost and buck mode. * Connect FB and VSENSE pin resistive dividers to the (+) terminals of COUT and signal ground. If a small VSENSE decoupling capacitor is used, it should be as close as possible to the LTC3785 GND pin. * Route ISVIN and ISSW1 leads together with minimum PC trace spacing. Ensure accurate current sensing with Kelvin connections across MOSFET A or sense resistor. * Route ISVOUT and ISSW2 leads together with minimum PC trace spacing. Ensure accurate current sensing with Kelvin connections across MOSFET D or sense resistor. * Connect the feedback network close to IC, between the VC and FB pins.
3785f
W
U
U
17
LTC3785 TYPICAL APPLICATIO U
VIN 2.7V TO 10V CVCC 4.7F VCC ISVIN VSENSE 270pF R1 205k R2 121k 1.3k FB 12k 1nF VC RT RT 59k MODE RILSET 42.2k ILSET CCM GND ISVOUT TG2 CMDSH-3 VBST2 SW2 ISSW2 BG2 CB 0.22F COUT 100F MC MD OPTIONAL D2 VOUT 3.3V 3A TG1 CMDSH-3 VBST1 SW1 ISSW1 VDRV BG1 LTC3785 CA 0.22F OPTIONAL D1 MB L1 4.7H MA CIN 22F MA = MB = MC = MD = 1/2 Si7940DY L1 = SUMIDA CE123-4R6 D1 = D2 = PMEG2020EJ 9V REGULATED WALL ADAPTER
+
1nF
VIN RUN/SS
Li-Ion 2.7V TO 4.2V
124k
205k
3785 TA02
3785f
18
LTC3785 PACKAGE DESCRIPTIO U
UF Package 24-Lead Plastic QFN (4mm x 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.75 0.05 BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP PIN 1 NOTCH R = 0.20 TYP OR 0.35 x 45 CHAMFER 23 24 0.40 0.10 1 2 2.45 0.10 (4-SIDES)
(UF24) QFN 0105
4.50 0.05 2.45 0.05 3.10 0.05 (4 SIDES)
4.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6)
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 0.05 0.50 BSC
3785f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3785 TYPICAL APPLICATIO U
Li-Ion/9V Wall Adapter to 5V/2A
VIN 2.7V TO 10V CVCC 4.7F VCC ISVIN VSENSE 270pF 205k 1.3k FB 66.5k 12k 59k RT ISVOUT TG2 CMDSH-3 MODE 42.2k ILSET CCM GND VBST2 SW2 ISSW2 BG2 CB 0.22F COUT 100F MC MD OPTIONAL D2 1nF VC VOUT 5V 2A TG1 CMDSH-3 VBST1 SW1 ISSW1 VDRV BG1 LTC3785 CA 0.22F OPTIONAL D1 MB L1 4.7H MA CIN 22F MA = MB = MC = MD = 1/2 Si7940DY L1 = SUMIDA CE123-4R6 D1 = D2 = PMEG2020EJ 9V REGULATED WALL ADAPTER
+
1nF
VIN RUN/SS
Li-Ion 2.7V TO 4.2V
124k
205k
3785 TA03
RELATED PARTS
PART NUMBER LTC3440 LTC3441 LTC3442 LTC3443 LTC3444 LTC3531 LTC3531-3 LTC3531-3.3 LTC3532 LTC3533 LTC3780 DESCRIPTION 600mA IOUT, 2MHz, Synchronous Buck-Boost DC/DC Converter 1.2A IOUT, 1MHz, Synchronous Buck-Boost DC/DC Converter 1.2A IOUT, 2MHz, Synchronous Buck-Boost DC/DC Converter 1.2A IOUT, 600kHz, Synchronous Buck-Boost DC/DC Converter 500mA IOUT, 1.5MHz Synchronous Buck-Boost DC/DC Converter 200mA IOUT, Synchronous Buck-Boost DC/DC Converter COMMENTS VIN: 2.5V to 5.5V, VOUT: 2.5V to 5.5V, IQ = 25A, ISD < 1A, MS, DFN Packages VIN: 2.4V to 5.5V, VOUT: 2.4V to 5.25V, IQ = 25A, ISD < 1A, DFN Package VIN: 2.4V to 5.5V, VOUT: 2.4V to 5.25V, IQ = 35A, ISD < 1A, DFN Package VIN: 2.4V to 5.5V, VOUT: 2.4V to 5.25V, IQ = 28A, ISD < 1A, MS Package VIN: 2.7V to 5.5V, VOUT: 0.5V to 5.25V, Optimized for WCDMA RF Amplifier Bias VIN: 1.8V to 5.5V, VOUT: 2V to 5V, IQ = 35A, ISD < 1A, MS, DFN Packages VIN: 2.4V to 5.5V, VOUT: 2.4V to 5.25V, IQ = 35A, ISD < 1A, MS, DFN Packages
500mA IOUT, 2MHz, Synchronous Buck-Boost DC/DC Converter
2A Wide Input Voltage Synchronous Buck-Boost DC/DC Converter VIN: 1.8V to 5.5V, VOUT: 1.8V to 5.25V, IQ = 40A, ISD < 1A, DFN Package High Efficiency, Synchronous, 4-Switch Buck-Boost Controller VIN: 4V to 36V, VOUT: 0.8V to 30V, IQ = 1.5mA, ISD < 55A, SSOP-24, QFN-32 Packages
3785f LT 0907 * PRINTED IN USA
20 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2007

▲Up To Search▲

Price & Availability of LTC3785

	To Download LTC3785 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .